1. Field of the Invention
The present invention relates to a semiconductor device including a memory cell having a composite gate structure or a semiconductor device including a stacked memory cell capacitor and a method of fabricating the same.
2. Description of the Related Art
Conventionally, several improvements have been made to improve the write and erase characteristics of a memory cell of an EEPROM or the like having a floating gate structure or a memory cell capacitor.
As an example, in prior art disclosed in Japanese Patent Laid-Open No. 5-110107, at least a portion of a polysilicon film as a floating gate electrode is formed by CVD under conditions by which a larger number of fine undulations are formed on the surface of the floating gate electrode, and an insulating interlayer and a control gate electrode are formed along the undulations on the surface of the floating gate electrode.
These fine undulations increase the capacitance between the floating gate electrode and a control gate electrode. When voltage drop in which the voltage applied to the control gate electrode decreases occurs, these undulations efficiently act on the floating gate electrode to improve the write and erase characteristics.
Also, in prior art disclosed in Japanese Patent Laid-Open No. 5-55605, a recess is formed in substantially the center of a floating gate electrode to increase the capacitance between the floating gate electrode and a control gate electrode. Consequently, an effect similar to the effect of the above prior art is achieved.
The capacitance of a memory cell capacitor can also be increased by forming undulations on the surface of a lower electrode.
For example, Japanese Patent Laid-Open No. 5-243515 has described a method of increasing the charge storage amount by forming a rectangular or cylindrical trench in a lower electrode of a stacked memory cell capacitor.
Unfortunately, the above-mentioned prior arts have the following problems.
First, in the prior art disclosed in Japanese Patent Laid-Open No. 5-110107, the fine undulations on the floating gate electrode are formed under specific conditions by CVD. Therefore, the fabrication steps are complicated to set the CVD conditions. Additionally, since these undulations are very fine, the effect of increasing the capacitance is not satisfactory.
In the prior art disclosed in Japanese Patent Laid-Open No. 5-55605, the recess is formed in substantially the center of the floating gate electrode after a polysilicon film serving as the floating gate electrode is formed. Therefore, it is unavoidable to complicate the fabrication steps and increase the number of the fabrication steps. Also, the end point of etching for forming the recess is difficult to determine. Accordingly, the recess may sometimes extend through the polysilicon film to separate the floating gate electrode.
In the prior art of a capacitor disclosed in Japanese Patent Laid-Open No. 5-243515, the trench is formed by etching after stacked polysilicon serving as the lower electrode is formed. Accordingly, the fabrication steps are complicated and the number of the fabrication steps is increased. Furthermore, the end point of the etching cannot be easily determined.